The present invention relates to nonvolatile memory apparatuses such as EEPROM (Electrically Erasable Programmable Read Only Memory) and the like and microcomputers using the same.
FIG. 9 shows an example of an internal structure of a semiconductor apparatus having therein an EEPROM in accordance with the conventional technology. The semiconductor apparatus has an EEPROM block 214 and a sequencer circuit 202. The EEPROM block 214 includes an EEPROM 201, a sense amplifier circuit 212 and a step-up circuit 213. The EEPROM block 214 is controlled by signals provided externally of the semiconductor apparatus, such as, a signal on an EEPROM address bus 203 to designate address values of the EEPROM 201, a data signal inputted in or outputted from the EEPROM 201 through an EEPROM data bus 204, an enable signal 205 to determine whether or not the EEPROM block 214 itself is accessed, a program signal 206 to command writing data in the EEPROM 201, and an erase signal 207 to command erasing data from the EEPROM 201.
Here, the enable signal 205, the program signal 206 and the erase signal 207 are assumed to be in active state at their respective LOW level
Also, the EEPROM block 214 in the semiconductor apparatus is controlled by signals, such as an X-decoder enable signal 208, a Y-decoder enable signal 209, a sense amplifier enable signal 210, a step-up circuit enable signal 211, a program pulse signal 215 and an erase pulse signal 216, which are in active state at their HIGH level.
Here, let us consider a case where data is written in a specified address of the EEPROM 210. The data writing operation is described hereunder with reference to a timing chart at the time of writing shown in FIG. 10.
Each signal is in the following initial state. The enable signal 205, the program signal 206 and the erase signal 207 are at HIGH level, respectively. The X-decoder enable signal 208, the Y-decoder enable signal 209, the sense amplifier enable signal 210 and the step-up circuit enable signal 211 are at LOW level, respectively. A signal at a predetermined level is inputted in the address bus 203, and data of a predetermined value from the EEPROM 201 is inputted in the data bus 204.
When data is written after the initial state, first, the enable signal 205 is changed to LOW level, and an address value where data is written is inputted in the address bus 203 Then, the program signal 206 is changed to LOW level, and the data to be written is inputted in the data bus 204. At this moment, the sequencer circuit 209, that receives the enable signal 205 and the program signal 206, generates the X-decoder enable signal 208, the Y-decoder enable signal 209, the sense amplifier enable signal 210 and the step-up circuit enable signal 211 in active state, and also generates the program pulse signal 215 in active state. These signals are used to perform data writing operation by the EEPROM 201. When each of the enable signals is generated and each of the pulses has a specified pulse width according to the characteristics specification of the EEPROM 201, desired data can be written at a specified address of the EEPROM 201.
When the data writing operation is completed, each of the signals is changed to non-active state by the sequencer circuit 202, and input signals externally provided are also changed to non-active state, the initial state is reset.
Data is erased, in a similar manner as the data writing, according to FIG. 11. When data is erased, the erase signal becomes to be in active state, and the data on the EEPROM 201 is erased.
In the conventional technology described above, the sequencer circuit 202 is indispensable in the semiconductor apparatus. The signals generated by the sequencer circuit 202 must be generated at the timings shown in FIG. 10. To normally write data in the EEPROM 201, the signals must be precisely generated at signal generation timings that are close to the specification timings as much as possible. Therefore, the circuit structure of the sequencer circuit 202 becomes complex because signal delays must be precisely generated, with the result that the size of the circuit becomes larger. As a result, substantial verification and examination are required to obtain a satisfactory sequencer circuit 202, resulting in a longer development period. Also, there is a drawback that debugging is difficult in the stage of product development.
Furthermore, when the semiconductor apparatus has a structure in which all EEPROM control signals are manipulated from outside of the semiconductor apparatus, problems occur. For example, the number of terminals of the semiconductor apparatus increases, the chip integration deteriorates due to increased wiring regions, and the chip area increases. Certain measures, for example, mounting an oscillation circuit in the circuit structure, or inputting oscillation signals from outside of the semiconductor apparatus, are required to accurately obtain time delays of signals. In this case, another circuit for processing the oscillation signals has to be added to the semiconductor apparatus chip. This is not preferable when low cost products are to be supplied to the market.
Accordingly, an object of the present invention is to provide a programmable nonvolatile memory apparatus and a microcomputer using the same without mounting a built-in sequencer circuit that has a large device size and therefore takes a long time for verification, and is difficult in debugging.
Another object of the present invention is to provide a nonvolatile memory apparatus and a microcomputer using the same in which programming is possible without mounting a built-in sequencer circuit, the number of external terminals is reduced and the internal wiring area is reduced.
A still another object of the present invention is to provide a nonvolatile memory apparatus in which a register for controlling a nonvolatile memory is provided therein, but address values of the register and address values of the nonvolatile memory are prevented from overlapping with one another without having to enlarge the address area.
A further object of the present invention is to provide a microcomputer that has a reduced circuit size in which data required for programming can be inputted either in a parallel input mode or a serial input mode.
A nonvolatile memory apparatus in accordance with the present invention has a nonvolatile memory in which a programming mode and a normal reading mode are set; and a register connected to the nonvolatile memory. When the programming mode is set, a plurality of data necessary for execution of the programming mode is supplied to the register, and each of the data is read out from the register and supplied to the nonvolatile memory. Accordingly, a sequencer circuit is not required in the nonvolatile memory apparatus as various timing signals are also provided by the register, and therefore the circuit structure becomes simpler compared with the prior art.
Further, the programming mode may includes, in addition to the data rewriting operation, an operation of rewriting data and an operation of erasing data. When each of the operations is executed, address data, rewriting data and control data required for the operation are supplied to the register, and each of the data is read out from the register, to thereby execute programming of the nonvolatile memory.
The register may include a plurality of flip-flops. Control data is supplied to and read from the plurality of flip-flops so that a plurality of control timing signals required for execution of the programming mode are supplied to the nonvolatile memory. In this manner, the control timing signals are outputted from the flip-flops. As a result, the circuit is substantially simplified compared with the conventional sequencer circuit.
At least one of the pluralities of control timing signals has a logic in active state that is different from the others As a result, data stored in the nonvolatile memory is not destroyed even when all of the control timing signals are at HIGH or LOW when the power is turned on.
The nonvolatile memory apparatus of the present invention further includes an input/output apparatus so that data to be supplied to the register can be inputted through the input/output apparatus from outside of the apparatus.
A microcomputer in accordance with the present invention comprises a nonvolatile memory in which a programming mode and a normal reading mode are set; a register connected to the nonvolatile memory; and a central processing unit that accesses the nonvolatile memory in the normal reading mode. When the programming mode is set, data necessary for execution of the programming mode is supplied to the register, and each of the data is read out from the register and supplied to the nonvolatile memory.
The microcomputer neither requires a sequencer within the microcomputer because various timing signals are also provided from the register. As a result, the circuit structure becomes simpler compared to the prior art.
The register preferably has address values and is addressable. Also, the address values of the register preferably exist in an address space that is different from an address space to which the nonvolatile memory is allocated. As a result, the microcomputer does not require preparing address values for the register within the same address space. Accordingly, this is advantageous for a microcomputer having a particularly small address area.
The microcomputer in accordance with the present invention may further comprises an input/output apparatus, wherein a signal to be supplied to the register are inputted through the input/output apparatus from outside. As a result, the address value of the register can be designated by the signal inputted through the input/output apparatus from outside. Further, a data value to be stored in the register are also inputted from outside through the input/output apparatus. Moreover, a data value stored in the register can be initialized by a signal inputted from outside through the input/output apparatus.
The input/output apparatus may include a parallel input/output apparatus to which a plurality of data are inputted in parallel. In this case, pluralities of data inputted through the parallel input/output apparatus are supplied to the register.
The parallel input/output apparatus may comprise a first switch that is selectively connected the parallel input/output apparatus to one of a data bus connected to the central processing unit and the register. The first switch connects the parallel input/output apparatus to the register in the programming mode so that pluralities of data inputted through the parallel input/output apparatus are supplied to the register. On the other hand, the first switch connects the parallel input/output apparatus to the data bus in the normal reading mode, so that various data can be inputted or outputted through the data bus and the parallel input/output apparatus by the control of the central processing unit.
Moreover, a second switch is preferably provided to selectively connect an input/output line of the nonvolatile memory to one of a data bus connected to the central processing unit and the register. The second switch connects the input/output line of the nonvolatile memory to the register in the programming mode, so that the central processing unit can supply to the register in parallel a plurality of data serially inputted through a serial input/output apparatus. On the other hand, in the normal reading mode, the input/output line of the nonvolatile memory is connected through the second switch to the data bus. As a result, the central processing unit can use the nonvolatile memory as a storage device such as a ROM.
The input/output apparatus may include a serial input/output apparatus to which a plurality of data are inputted in serial. In this case, the central processing unit supplies the plurality of data inputted in serial through the serial input/output apparatus to the register in parallel.
The input/output apparatus may include a serial input/output apparatus to which a plurality of data are inputted in serial in the serial input mode, and a parallel input/output apparatus to which the plurality of data are inputted in parallel in the parallel input mode. In the serial input mode, the plurality of data serially inputted through the serial input/output apparatus are supplied to the register in parallel by the central processing unit. In the parallel input mode, the plurality of data inputted through the parallel input/output apparatus are supplied to the register In this case, the first and second switches may also preferably be provided.